rev. 2.2 - 4/27/98 1 1 2 3 4 5 6 7 8 9 10 11 12 features n high-speed access times com?: 7, 8, 10, 12 and 15 ns industrial: 8, 10, 12 and 15 ns n low power operation (typical) - pdm41257sa active: 400 mw standby: 150 mw - pdm41257la active: 350 mw standby: 25 mw n single +5v ( 10%) power supply n ttl compatible inputs and outputs n packages plastic soj (300 mil) - so description the pdm41257 is a high-performance cmos static ram organized as 262,144 x 1 bit. writing to this device is accomplished when the write enable (we ) and the chip enable (ce ) inputs are both low. reading is accomplished when we remains high and ce goes low. the pdm41257 operates from a single +5v power supply and all the inputs and outputs are fully ttl- compatible. the pdm41257 comes in two versions, the standard power version pdm41257sa and a low power version the pdm41257la. the two versions are functionally the same and only differ in their power consumption. the pdm41257 is available in a 24-pin 300-mil plastic soj for surface mount applications. a0 a17 ce we addresses decoder memory matrix column i/o d in d out functional block diagram pdm41257 256k static ram 256k x 1-bit
pdm41257 2 rev. 2.2 - 4/27/98 truth table note: 1. h = v ih , l = v il , x = don? care absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. exposure to absolute maxi- mum rating conditions for extended periods may affect reliability. 2. appropriate thermal calculations should be performed in all cases and speci?ally for those where the chosen package has a large thermal resistance (e.g., tsop). the calculation should be of the form : t j = t a + p * q ja , where t a is the ambient tempera- ture, p is average operating power and q ja the thermal resistance of the package. for this product, use the following q ja value: soj: 83 o c/w we ce d out mode x h hi-z standby hld out read l l hi-z write symbol rating com l. ind. unit t term terminal voltage with respect to v ss ?.5 to +7.0 ?.5 to +7.0 c t bias temperature under bias ?5 to +125 ?5 to +135 c t stg storage temperature ?5 to +125 ?5 to +150 c p t power dissipation 1.0 1.0 w i out dc output current 50 50 ma t j maximum junction temperature (2) 125 145 c soj 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a0 a1 a2 a3 a4 a5 a6 a7 a8 d out we vss vcc a17 a16 a15 a14 a13 a12 a11 a10 a9 d in ce pin con?uration pin description name description a17-a0 address inputs d in data input d out data output we write enable input ce chip enable input v cc power (+5v) v ss ground
pdm41257 rev. 2.2 - 4/27/98 3 1 2 3 4 5 6 7 8 9 10 11 12 recommended dc operating conditions dc electrical characteristics (v cc = 5.0v 10%) note: 1. v il (min) = ?.0v for pulse width less than 20 ns. power supply characteristics shaded area = preliminary data note: all values are maximum guaranteed values. symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v v ss supply voltage 0 0 0 v commercial ambient temperature 0 25 70 c industrial ambient temperature ?0 25 85 c pdm41257sa pdm41257la symbol parameter test conditions min. max. min. max. unit i li input leakage current v cc = max., v in = v ss to v cc com?/ ind. 55 55 m a i lo output leakage current v cc = max., ce = v ih , v out = v ss to v cc com?/ ind. 55 55 m a v il input low voltage ?.5 (1) 0.8 ?.5 (1) 0.8 v v ih input high voltage 2.2 6.0 2.2 6.0 v v ol output low voltage i ol = 8 ma, v cc = min. i ol = 10 ma, v cc = min. 0.4 0.5 0.4 0.5 v v v oh output high voltage i oh = ? ma, v cc = min. 2.4 2.4 v -7 -8 -10 -12 -15 symbol parameter power com l. com l. ind. com l. ind. com l. ind. com l. ind. units i cc operating current ce = v il sa 210 200 210 190 200 180 190 170 180 ma f = f max = 1/t rc v cc = max i out = 0 ma la 190 180 190 170 180 160 170 150 160 ma i sb standby current ce = v ih sa 90 80 80 70 70 60 60 50 50 ma f = f max = 1/t rc v cc = max la 90 80 80 70 70 60 60 50 50 ma i sb1 full standby current ce 3 v cc ?0.2v sa 20 20 20 20 20 20 20 20 20 ma f = 0 v cc = max v in 3 v cc ?0.2v or 0.2v la 5 55555555ma
pdm41257 4 rev. 2.2 - 4/27/98 capacitance (1) (t a = +25 c, f = 1.0 mhz) note: 1. this parameter is determined by device characterization but is not production tested. ac test conditions symbol parameter conditions max. unit c in input capacitance v in = 0v 8 pf c out output capacitance v out = 0v 8 pf input pulse levels v ss to 3.0v input rise and fall times 3 ns input timing reference levels 1.5v output reference levels 1.5v output load see figures 1 and 2 figure 1. output load equivalent figure 2. output load equivalent (for t lzce , t hzce , t lzwe , t hzwe ) +5v 480 w 255 w d out 30 pf +5v 480 w 255 w d out 5 pf 5 4 3 2 1 0 0 30 60 90 120 typical delta t aa vs capacitive loading additional lumped capacitive loading (pf) delta t aa - ns
pdm41257 rev. 2.2 - 4/27/98 5 1 2 3 4 5 6 7 8 9 10 11 12 read cycle no. 1 (1) read cycle no. 2 (2) ac electrical characteristics shaded area = preliminary data. notes referenced are after data retention table. description -7 (6) -8 (6) -10 (6) -12 -15 read cycle sym min. max. min. max. min. max. min. max. min. max. units read cycle time t rc 7 8 101215 ns address access time t aa 7 8 10 12 15 ns chip enable access time t ace 7 8 10 12 15 ns output hold from address change t oh 3 3333ns chip enable to output in low z (3, 4, 5) t lzce 5 5555ns chip disable to output in high z (3, 4, 5) t hzce 5 5 10 10 10 ns chip enable to power up time (4) t pu 0 0000ns chip disable to power down time (4) t pd 7 8 10 12 15 ns t rc t aa t oh previous data valid d out addr data valid t rc t ace t aa t lzce t hzce t lzoe t hzoe t aoe addr ce d out data valid
pdm41257 6 rev. 2.2 - 4/27/98 write cycle no. 1 (write enable controlled) write cycle no. 2 (chip enable controlled) ac electrical characteristics shaded area = preliminary data description -7 (6) -8 (6) -10 (6) -12 -15 write cycle sym min. max. min. max. min. max. min. max. min. max. units write cycle time t wc 7 8 101215 ns chip enable to end of write t cw 7 8 101012 ns address valid to end of write t aw 7 8 101012 ns address setup time t as 0 0000ns address hold from end of write t ah 0 0000ns write pulse width t wp 7 8 101011 ns data setup time t ds 6 7778ns data hold time t dh 0 0000ns write disable to output in low z (4,5) t lzwe 0 0000ns write enable to output in high z (4,5) t hzwe 33333ns t wc t aw t cw t ah t as t hzwe high z data valid t lzwe t ds t dh addr ce t wp we d in d out t wc t aw t cw t wp t ds data valid t dh t as addr d in undefined don't care t ah ce we
pdm41257 rev. 2.2 - 4/27/98 7 1 2 3 4 5 6 7 8 9 10 11 12 low v cc data retention waveform data retention electrical characteristics (la version only) notes: (for three previous electrical characteristics tables) 1. the device is continuously selected. chip enable is held in its active state. 2. the address is valid prior to or coincident with the latest occuring chip enable. 3. at any given temperature and voltage condition, t hzce is less than t lzce . 4. this parameter is sampled. 5. the parameter is tested with cl = 5 pf as shown in figure 2. transition is measured 200 mv from steady state voltage. 6. v cc = 5v 5%. ordering information symbol parameter test conditions min. typ. max. unit v dr v cc for retention data 2 v i ccdr data retention current ce 3 v cc ?0.2v v in 3 v cc ?0.2v or 0.2v v cc = 2v 95 500 m a v cc = 3v 350 750 m a t cdr chip deselect to data retention time 0 ns t r (4) operation recovery time t rc ns don't care v cc v v ih il t cdr v t r 4.5v 4.5v data retention mode ce dr v dr device type power speed package type process temp. range preferred shipping container commercial (0 to +70 c) industrial (?0 c to +85 c) 7 commercial only 8 10 12 15 sa standard power la low power blank i a automotive ( ?0 c to +105 c) blank tubes tr tape & reel ty tray pdm41257 - 256k (256kx1) static ram xxxxx x xx x x x so 24-pin 300-mil plastic soj faster memories for a faster world
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